The present invention, in some embodiments thereof, relates to a gain cell with internal feedback and, more particularly, but not exclusively, to a five-transistor gain cell with internal feedback.
Modern microprocessors and other VLSI systems-on-chip (SoCs) implemented in aggressively scaled CMOS technologies are characterized by high leakage currents, and require an increasing amount of embedded memory [ref. 1]. Such embedded memory, typically implemented as 6-transistor (6T)-bitcell SRAM macrocells, not only consume an ever growing share of the total silicon area but also significantly contributes to the leakage power of the system. (The leakage power is a large share of the total power budget in deeply scaled CMOS nodes.) Unfortunately, besides several advantages like fast access speed and robust, static data retention, the 6T SRAM bitcell is relatively large, exhibits several leakage paths, and has dramatically increased failure rates under voltage scaling.
Additionally, in ultra-low power (ULP) applications the silicon area is often dominated by embedded memories, which are the main consumers of both the static and dynamic power in these applications. Supply voltage scaling down to the sub-threshold region is widely used to significantly reduce both the static and dynamic power dissipation of ULP applications. However, embedded memories, typically implemented with SRAM, have been the limiting factor for aggressive voltage scaling, since the conventional 6T SRAM bitcell becomes unreliable at near-threshold operating voltages.
Gain-cell embedded DRAM (GC-eDRAM) is an alternative to conventional SRAM memories, as it is fully logic-compatible, offers smaller area, and can consume lower standby power than SRAM. GC-eDRAM may be compatible with sub-threshold operation in mature process nodes, such as 180 nm technology. However, GC-eDRAM requires periodic power-hungry refresh cycles to retain its data.
The Data Retention Time (DRT) of GC-eDRAMs is the maximum time interval from writing a data level into the bitcell to still being able to correctly read out the written level. The DRT is primarily limited by the level set by the initial charge stored in the bitcell and the leakage currents that degrade this level. Gain cell implementations in mature technology nodes, such as 180 nm, have been shown to exhibit high DRTs of tens to hundreds of milliseconds [ref. 4,5]. However conventional 2T gain cells in newer technology nodes, such as 65 nm, display much lower DRTs of only tens of microseconds [ref. 6]. The lower DRT is a direct consequence of the substantially higher leakage currents which result in a much faster deterioration of the stored levels [ref. 5]. Depending on the type of write transistor (WT), one of the data levels has a much higher retention time than the other (e.g. data ‘1’ for a PMOS WT and data ‘0’ for a NMOS WT) [ref. 6]. However, when determining the refresh frequency, one must consider the deterioration of the weaker data level under worst-case conditions, i.e. when the write bit line (WBL) is driven to the opposite level of the stored data during retention periods. While mature technology nodes offered sufficient retention times at low operating voltages, process scaling has led to a substantial decrease in retention time, limiting the operating voltage of GC-eDRAM in sub-100 nm technologies to the near-threshold or even above-threshold domain.